AdAM: Adaptive Approximate Multiplier for Fault Tolerance in DNN Accelerators

Parallel Chaos-based image encryption algorithm: High-Level Synthesis and FPGA implementation

A Comprehensive Survey on Model Quantization for Deep Neural Networks in Image Classification

Propounding First Artificial Intelligence Approach for Predicting Robbery Behavior Potential in an Indoor Security Camera

Logarithm-approximate floating-point multiplier

Design of approximate adder and multiplier for image processing applications

Data-driven and Knowledge-based Algorithms for Gene Network Reconstruction on High-dimensional Data

Code Acceleration Using Memristor-Based Approximate Matrix Multiplier: Application to Convolutional Neural Networks

Towards memristor-based approximate accelerator: application to complex-valued FIR filter bank

Parallel Algorithms for Inferring Gene Regulatory Networks: A Review

Vulnerability Analysis of Adder Architectures Considering Design and Synthesis Constraints

Memristor-based approximate matrix multiplier

Fast and accurate architectural vulnerability analysis for embedded processors using Instruction Vulnerability Factor

Reliability aware throughput management of chip multi-processor architecture via thread migration

Reliability-aware simultaneous multithreaded architecture using online architectural vulnerability factor estimation

An analytical method for reliability aware instruction set extension

Adaptive fault-tolerant DVFS with dynamic online AVF prediction

SHIELD: PSO-Based Hardware Trojan Detection for Efficient and Low-Cost Defense

SynAssert: Automated Synthesis of CSCA Leakage Patterns into Cost-Effective Security Assertions

Ultra-Low-Latency QCA Adder Design Using an Innovative Carry Generato

Genie: Genetic algorithm-based reliability assessment methodology for deep neural networks

Reliability-Aware Performance Optimization of DNN HW Accelerators through Heterogeneous Quantization

A Double Approximate Neural Hardware Accelerator

PATROL: An Evolutionary APproach to Automatic Test Pattern Generation for Hardware TROjan Detection Leveraging PSO-GA Hybrid Techniques

FORTUNE: A Negative Memory Overhead Hardware-Agnostic Fault TOleRance TechniqUe in DNNs

Zero-Memory-Overhead Clipping-Based Fault Tolerance for LSTM Deep Neural Networks

Automatic High Functional Coverage Stimuli Generation for Assertion-based Verification

AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators

Hardware Implementation of a Chaos Based Image Encryption Using High-Level Synthesis

Significantly improving human detection in low-resolution images by retraining YOLOv3

An ultra-fast multi-objective optimization algorithm for VLIW architecture

Reliability-aware Cross-Layer Custom Instruction Screening

Vulnerability Analysis For Custom Instructions

CIVA: Custom Instruction Vulnerability Analysis Framework

Instruction reliability analysis for embedded processors

Energy/throughput trade-off in a fully asynchronous NoC for GALS-based MPSoC architectures

Reliability considerations in dynamic voltage and frequency scaling schemes

Analysis of single-event effects in embedded processors for non-uniform fault tolerant design